This invention relates to a method for translating instructions in a computer system.
The invention is particularly concerned with a computer system in which source code instructions are translated into target code instructions for execution on a particular processor. This may be required, for example, where one processor is being used to emulate another, in which case the instructions for the processor being emulated must be translated into instructions for the emulating processor.
One approach, referred to as interpretation, is to create a software model of the processor being emulated. This model operates by reading each target instruction, decoding it, and selecting one of a number of sequences that perform the same function as the instruction being emulated. This fetch/decode/execute sequence is repeated for each source code instruction in turn.
A more efficient approach is to translate a block of source code instructions, rather than a single instruction. That is, the source code is divided into blocks, and each source code block is translated into a block of target code instructions, functionally equivalent to the source code block. Typically, a block has a single entry point and one or more exit points. The entry point is the target of a source code jump, while the (or each) exit is a source code jump.
Translating blocks is potentially much more efficient, since it provides opportunities for eliminating redundant instructions within the target code block, and other optimisations. Known optimising compiler techniques may be employed for this purpose. To increase efficiency further, the target code blocks may be held main memory and/or a cache store, so that they are available for re-use if the same section of code is executed again, without the need to translate the block.
However, the process of designing such a translator is very complex, and it is difficult to avoid errors in translation. One object of the present invention is to provide an improved translation technique, which reduces such errors.
Another object of the present invention is to provide a novel technique for improving the efficiency of block-oriented code translation.
According to the invention, in a computer system, a method of translating source code instructions into target code instructions comprises the steps:
(a) analysing an existing interpreter to identify sequences that implement individual source code instructions and storing those sequences as templates; and
(b) for each instruction in an input block of source code instructions, selecting an appropriate template for that source code instruction and appending this template to an output block of target code instructions.
It can be seen that this uses an existing interpreter as the basis for building a translation mechanism. Assuming that the existing interpreter is already fully validated, the possibility of errors in the templates is correspondingly reduced. In effect, the invention provides a way of xe2x80x9cleveragingxe2x80x9d an existing interpreter.
According to another aspect of the invention, in a computer system, a method of translating source code instructions into target code instructions comprises the steps:
(a) providing a plurality of templates, which implement respective source code instructions, without implementing predetermined sub-functions within the source code instructions;
(b) for each instruction in an input block of source code instructions, selecting an appropriate template for that source code instruction and appending this template to an output block of target code instructions;
(c) analysing the source code block to determine the net effect of the non-implemented sub-functions; and
(d) planting code in the output block to achieve this net effect.
It can be seen that this provides templates from which sub-functions have been eliminated, and then re-introduces the effect of these eliminated sub-functions on a per-block basis. This gives opportunities for optimisation by allowing sub-functions to be coalesced or simply omitted where they are redundant. In particular, a number of address range checks may be merged into a single check.
One embodiment of the invention will now be described by way of example with reference to the accompanying drawings.